Project of IPv6 Router with FPGA Hardware Accelerator
نویسندگان
چکیده
Packet processing is pipelined. A packet flows through the FPGA and memories. An incoming packet is received by the Input Packet Buffer and passed to the Header Field Extractor. The HFE pushes the body of the packet into the dynamic memory. Meanwhile, it parses its headers and creates a Unified-header and a structure reflecting actual arrangement of the headers. The Unified-header is a fixed structure containing information relevant for routing and filtering decisions. The Lookup Processor (LUP) processes the Unified-header performing a lookup nanoprogram. The lookup nanoprogram is kept in CAM and SRAM. Using CAM is fast, unfortunately, IPv6 requires nearly 600 bits to check. Widest available CAMs have less than 300 bits, therefore a combination of CAM search and lookup instructions (conditional jumps) is used.
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